The following disclosure relates to semiconductor manufacturing methods. In particular, the following disclosure relates to method for forming a contact to a semiconductor device.
For advanced semiconductor nodes, the scaling of devices in accordance with Moore's Law has driven the contacted poly pitch (CPP) (i.e., the minimum center-to-center space between gates of adjacent transistors) to less than about 100 nm. As a result, contacts to the source or drain of such transistors must fit within the remaining space between adjacent gates without shorting the gate to the drain. To achieve this, methods such as double or triple-patterning of source/drain contacts have been utilized.
Multiple-patterning techniques require additional masks and manufacturing overhead over single-patterning techniques. Moreover, the use of additional masks reduces overlay (OVL) control between source/drain contacts, the source or drain to which the contact aligns, and adjacent features such as the gate of the transistor from which the contact must remain electrically isolated to insure yield. Other techniques such as self-aligned contact formation can reduce OVL degradation associated with multiple-patterning techniques, but require additional layers in the transistor device stack form proper contact formation.